For most of the radar applications and RF test & measurements, you would need an RF signal generator which would act as the source. The RF signal generator you were to use in your work should have some basic properties such as:
- Matched to 50Ω
- Tunable output frequency
- Tunable output power level
- low phase noise
In order to achieve all these specs, a Voltage Controlled Oscillator (a.k.a. VCO) in a Phase-Locked Loop (PLL) is necessary. Luckily for us, you can find plenty of VCOs with PLL built-in a single chip from many manufacturers up to a few ten GHz. However, with increasing output frequency, the price increases rapidly. Therefore, for a micro-budget project, it is necessary to limit yourself up to a certain frequency. Most of the RF signal generators are at least several thousand dollars and for any minor extra feature you would like to have, the price goes even higher. Although we have several nice RF signal generators in our laboratory, I wanted to build myself one, as it would probably be a nice experience.
Homemade RF Signal Generator
First of all, I’ve started my search for a suitable frequency synthesizer IC. There were many ICs up to 6-7GHz and I decided to go for an IC up to 6GHz or so. There were several reasons why I chose my upper frequency limit to be 6GHz. First of all, the price of the ICs increase rapidly above 6 GHz range. Many manufacturers have ICs up to 6GHz, which raises the competition and lowers the prices. At higher frequencies however, the number of available ICs are limited and the prices are way over my budget for this project.
Moreover, in order to generate high frequency signals with minimal loss, I would need a high performance laminate, such as Rogers Duroid® Laminates by Rogers Corp. However, they are quite expensive and it is hard to find a manufacturer which offers Rogers laminates. Even if they do…well, it’s expensive. So I’ve decided to use some FR4 process at the cost of reduced high frequency performance but greatly reduced cost.
The last, but not the least, reason I’ve picked 6 GHz as my upper limit is that, the presence of a 6GHz handheld VNA in our lab. Most communication systems are up to several GHz and anything above this frequency is mostly for scientific or military-related projects. If our 6GHz handheld VNA in our lab is enough for most of our needs, then a palm-sized RF signal generator up to 6GHz should also be fine.
VCO with PLL – The core of RF Signal Generator
Our pick of VCO with PLL is very important. I’ve decided to go for Analog Devices ADF4355 in this system. Analog Devices offer great datasheets, technical articles and design sources. Also, they are usually quick to respond to sample requests. Yet, they don’t ship samples to Turkey. Luckily for me, I’ve been able to get some samples as a favor from an old friend. Using the datasheet provided by Analog Devices, I’ve finished the schematic level design of my RF signal generator pretty quickly. Besides, I’ve decided to use 3V3 version to get rid of an extra LDO to reduce the cost further. The properties of ADF4355-3 are as follows:
- RF output frequency range: 51.5625 MHz to 6600 MHz
- Fractional-N synthesizer and integer-N synthesizer
- High resolution 38-bit modulus
- Low phase noise, voltage controlled oscillator (VCO)
- Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
- All power supplies: 3.3 V
- Logic compatibility: 1.8 V
- Programmable dual modulus prescaler of 4/5 or 8/9
- Programmable output power level
- RF output mute function
- 3-wire serial interface
- Analog and digital lock detect
ADF4355-3 needs to be programmed using an SPI-compatible interface, which would need a MCU or something alike. Eitherway, I’ve decided to focus on RF hardware and connected those pins to headers, to be used later from an outside MCU or FPGA.
Schematic Level Design
I’ve decided to add some extra gain stage to the output of my PLL IC. Although it seems like the output power level would be over P1dB at high frequencies. In order to have a fixed output power over a wide-frequency range, it is necessary to use a power detector and an adjustable step attenuator, both to be controlled by some MCU.
RF signal source with tunable output power
However, using such a structure would increase the level of complexity, and as I’ve decided to do PLL programming from a different source already, I decided to leave them out too. It would be the first of many iterations, so taking some small steps at first might be better. Moreover, it would be easier to debug with a limited number of components whereas it could easily turn into a nightmare if I were to implement many things at first.
Turning Schematic into Something Physical – Drawing the Layout
I use EAGLE to draw the layouts due to several reasons. First of all, it is quite popular, which makes it easy to find what you need online, and the Digikey provides symbols and footprints for most parts. Moreover, there are many video tutorials and stuff like that to learn or improve yourself about using EAGLE.
So now, we need to connect our 2 LDOs, 1 Gain Block and 1 PLL to each other. The current consumption of blocks are mediocre, so I don’t personally believe it would be necessary to draw them extra thick to reduce the series resistance. Any capacitance to ground unwanted high-frequency components should be placed as close as possible to the respective pins. I’ve tried to place extra ground plane vias whereever possible. Also, I never used the sides with RF output during routing, to avoid any ground plane discontinuity.
When I’ve tried to connect my 50Ω transmission line to the chips, I’ve realised that they are too thin compared to my line. Unfortunately, EAGLE does not offer an easy way to draw tapered lines. However, after searching the topic a little bit, short thin lines are not a big problem as long as they are not comparable to wavelenght. Sımulations prove this to be true also. So, I’ve decided to give it a go. The devices I’ve used are matched to 50Ω internally, so if I were to measure my output matching with a VNA, I can easy observe if the matching is problematic or not.
I’ve tried to draw to board to minimize the board dimensions to further reduce the cost. For this project I wanted to work with OSHPark for PCB order and their 0.8mm 2oz option. I’ve also ordered some other PCBs from there, and still waiting for them to arrive. As they charge you for the total board area with no minimum area restrictions, it is wise to reduce the size as much as possible. As we have plenty of space, I’ve decided to write our lab and my collegues names on the board too. When I receive my PCBs, they should look like this.
So the layout is finished, and we’ve sent our PCB to fabrication. Is it over now? The exact opposite! We just took the first of many steps. As you can see, we have so many ICs which have exposed pad. Thou I’ve several stencils for some most common packages, I’ve decided to order a stencil custom-made for this board from OSHStencils. I’ve executed the BOM script of eagle to provide me a .txt file to check if we had all these SMD components in our lab. I’ve then ordered the missing ones from Digikey.
So, we are still waiting for the PCB and I’ve got all other components in my cubboard. After we manage to solve the programming of PLL issue, we are planning to build the next generation of it which would include adjustable output power option, and probably it would be better because of many issues we may notice with this one. I’ll also write about the other PCB which we ordered. I’ll try to keep you guys updated.